The present invention relates to a simplified process for forming retrograde dopant distributions in integrated circuit structures, that is, dopant distributions which increase in a vertically inward or downward direction from the surface of a layer or body such as a semiconductor substrate. As used here in reference to the present invention, the word "retrograde" also connotes a controlled dopant profile.
The potential advantages of a retrograde dopant distribution in semiconductor substrates are several, particularly in CMOS integrated circuit structures. The advantages are well-known and include the potential for increased device packing density and decreased susceptibility to latchup. It is believed there are available basically three approaches for forming a retrograde dopant profile. The techniques, namely, high energy implants (greater than about 200 keV), buried epitaxial layers, and outdiffusion, can be used separately or in combination.
An example of retrograde processing techniques is disclosed in Manoliu et al, "High-Density and Reduced Latchup Susceptibility of CMOS Technology for VLSI", IEEE Electron Device Letters, Vol. EDL-4, No. 7, July, 1983, pp. 233-235. Manoliu et al. uses the combination of a first implant in a doped substrate and a later implant in an undoped epitaxial layer. The well formation process is concluded with an anneal cycle. The specific CMOS structure and epitaxial buried layer retrograde p-well structure reportedly increases circuit density by reducing the minimum n.sub.+ -p.sup.+ spacing while decreasing latchup susceptibility.
Chen, "Quadruple-Well CMOS for VLSI Technology", IEEE Transactions on Electron Devices, Vol. ED-31, No. 7, July 1984, pp. 910-919, describes a process for forming a retrograde, quadruple-well CMOS structure. The n-well and p-well retrograde doping profiles each require multiple doping steps. Essentially, the structure is a two-well structure in which deep n-type and p-type wells are separated by respective shallow n-type and p-type wells or channel stops. The shallow wells are implanted through a peripheral field oxide during the deep well implantation. Overall, the Chen process involves, first, forming deep-well windows in a planar field oxide. The p-well region is masked and a high energy phosphorus implant at 290 keV is done in the presence of the mask to define the deep n-well and the adjacent shallow n-type channel stop under the oxide. The n-well is then counter-doped with boron for threshold voltage adjustment.
After the two-implant-step formation of the retrograde n-well, the n-well is masked and a multiple doping sequence is applied to provide the p-well retrograde profile. Initially, a 120 keV boron implant is used to form a relatively deep p-well, and the adjacent shallow p-type channel stop under the oxide. Phosphorus counterdoping adjusts the n-channel threshold voltage. Then, a deep, high energy 340 keV boron implant provides the deep retrograde p-well profile which is used to eliminate latchup. The counter-doping aspects of the process i.e., the combination of high energy implants and opposite conductivity low energy counter-doping, are also disclosed in Chen, U.S. Pat. No. 4,411,058, issued Oct. 25, 1983.
The outdiffusion of semiconductor dopants from the surfaces of silicon, mentioned above, is another well-known phenomenon, one that in the past has produced undesirable results. For example, outdiffusion from the front and rear major surfaces of semiconductor wafers leads to both macro-outdoping and micro-autodoping. Various process techniques are used to eliminate or decrease the effects of outdiffusion, including two-step processing using process interruption and/or high and low temperatures, and sealing of wafer surfaces with a mask such as silicon, silicon dioxide or silicon nitride.
Recently, outdiffusion has been used advantageously to provide a retrograde dopant distribution, but the process techniques for implementing the outdiffusion-caused retrograde dopant distribution typically are complex. For example, Steinmaier, U.S. Pat. No. 3,767,487 relates to the use of outdiffusion techniques to form selected, isolated retrograde surface-adjacent regions which are used as isolation wells for MOS or bi-polar devices. Referring to FIG. 1, the MOS integrated circuit process disclosed in the Steinmaier '487 patent involves forming a five-micron thick n-type epitaxial layer 11 on a p-type semiconductor 10; forming a thermal oxide masking layer 12 over the epitaxial layer having an aperture 13 which defines the p-well or isolation region; depositing a shallow p-well 14 in the surface of the epitaxial layer at the masked apertures using an oxidizing atmosphere to re-cover (not shown) the exposed substrate surface regions; etching the oxide mask to reexpose the epitaxial layer over part of the deposited impurity region beneath the masked windows; and outdiffusing the boron via the mask apertures 13 in a vacuum ampul containing silicon to provide the retrograde concentration in region 14. In particular, the vertical retrograde dopant concentration in region 14, that is, the relatively low surface concentration there, provides a high breakdown voltage for the NMOS device which is subsequently formed in the p-well 14. In addition, in the surface region 16 surrounding the well 14, the mask prevents outdiffusion, thereby providing a surface region 16 of relatively high doping concentration surrounding the retrograde well 14. This horizontal dopant concentration gradient is used to prevent short circuits between the epitaxial layer 11 and the subsequently formed NMOS device.
As is evident from the above description, in regard to small geometry, high density structures, the Steinmaier '487 retrograde p-well fabrication process suffers from several disadvantages in addition to complexity. The shallow retrograde p-well 14 does not appear to be capable of providing the desirable retrograde dopant gradient along the deep isolation trenches which are used in some CMOS structures. The adjacent n-well 17 is capped during the outdiffusion step and does not have a retrograde dopant concentration gradient. Furthermore, the lateral dopant concentration gradient at the periphery of the p-well 14 quite obviously limits the minimum dimension of, and spacing between, the wells. In short, the complex processing of the Steinmaier '487 patent is tailored to provide a p-well-only retrograde gradient and a lateral doping gradient that are inconsistent with small geometry, high density integrated circuits.
Shappir, U.S. Pat. No. 3,921,283 uses surface outdiffusion in the fabrication of dielectrically isolated MOSFET semiconductor devices. Referring to FIG. 2, in the illustrated process an n-type bulk substrate 20 is masked using an oxide 21-nitride 22 composite. Initially, the composite mask is used to etch trenches which are then filled with thermal oxide to provide a trench isolation structure for the NMOS active area 24 and the PMOS active area 25. Next, the mask 21-22 is removed from the NMOS device active area. The NMOS p-well 26 is then formed using both the trench oxide 23 and the mask 20-21 over the PMOS device 25 as implant/doping masks. The mask is retained over the n-well for the PMOS device active area and the semiconductor integrated circuit structure is heated in the presence of silicon powder to simultaneously indiffuse and outdiffuse boron p-well 26 to provide a retrograde dopant distribution in the p-well. There is no disclosure of forming a retrograde profile in n-well 28 or of doping this in combination with the retrograde p-well. In particular, there is no teaching of an a single mask, integrated, epitaxial process particularly suited for decreasing latchup susceptibility.
Vora, U.S. Pat. No. 4,032,372, issued June 28, 1977, forms bipolar and field effect transistors in individual, outdiffused, retrograde n-type wells or pockets which are formed in a semiconductor substrate. Initially, the surface region of the starting bulk substrate is doped with both arsenic and phosphorus to respective n.sup.+ concentrations of about 10.sup.20 and 10.sup.21 atoms/cc. A three micron thick p-type epitaxial layer is then formed over the substrate, and an oxide layer which serves as an outdiffusion cap (and subsequently as the field isolation oxide) is formed on the outer surface of the epitaxial layer. Then, the arsenic and phosphorus are outdiffused until the much faster diffusing phosphorus reaches the outer surface of the oxide capped epi layer, thereby forming an n-type phosphorus pocket which encloses an arsenic buried region within the p-type epi/bulk substrate.
The resulting retrograde vertical concentration gradient provides a relatively heavily doped bottom region for bipolar collector and subcollector structures, and a relatively lightly doped upper region for optimized field effect transistors. However, the vertical retrograde isolation wells or pockets of the Vora '372 patent require a relatively complex fabrication sequence involving the above-described two implant steps and the oxide capping layer, in addition to the epitaxial layer. The phosphorus and the arsenic outdiffusion heating step also establishes a lateral dopant concentration gradient that would undesirably increase the effective lateral dimensions and design spacing of the isolation pockets. The design spacing is increased still further for arsenic concentrations greater than about 10.sup.21 atoms/cc due to lateral spreading of the arsenic along the interface of the epitaxial layer and substrate, and requires the use of arsenic concentrations less than 10.sup.21 atoms/cc, or process compensation. Foremost, the process yields a retrograde distribution in only one of the two impurity regions. Because of these aspects, the Vora '372 retrograde process is believed to be limited to the specific disclosure of combined bipolar/field effect device fabrication, and to integrated circuit structures which require the specific combination of bipolar and FET structures at the expense of device close packing.
In view of the above discussion, it is a primary object of the present invention to implement a retrograde dopant distribution using simple process techniques.
It is another object to provide the above-described retrograde dopant distribution using process techniques which are readily incorporated into existing semiconductor fabrication processes.
It is still another object to provide a process for forming a retrograde dopant distribution, the steps of which are readily incorporated into standard CMOS fabrication sequences to provide advantages such as those listed in the Manoliu et al. article referenced above, including decreased susceptibility to latchup, and to do so for both p and n channel MOS devices without high energy implants, buried layers or complex processing. In addition, in regard to integrated circuit structures using trench dielectric isolation, it is an object to decrease susceptibility to inversion along the trench walls and to do so without high energy implants, buried layers or complex processing.